Operating Temperature -40°C~125°C
Packaging Tube
Published 2009
Series 74LV
JESD-609 Code e4
Part Status Obsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 20
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Additional Feature BROADSIDE VERSION OF 373
Subcategory FF/Latches
Technology CMOS
Voltage - Supply 1V~5.5V
Terminal Position DUAL
Peak Reflow Temperature (Cel) 260
Number of Functions 1
Supply Voltage 3.3V
Terminal Pitch 2.54mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74LV573
Pin Count 20
JESD-30 Code R-PDIP-T20
Qualification Status Not Qualified
Output Type Tri-State
Circuit 8:8
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 1V
Load Capacitance 50pF
Number of Ports 2
Number of Bits 8
Family LV/LV-A/LVX/H
Output Characteristics 3-STATE
Current - Output High, Low 16mA 16mA
Logic Type D-Type Transparent Latch
Output Polarity TRUE
Max I(ol) 0.008 A
Prop. Delay@Nom-Sup 29 ns
Independent Circuits 1
Delay Time - Propagation 24ns